(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to fabricate a bipolar junction transistor, (BJT), on a semiconductor substrate.
(2) Description of Prior Art
Bipolar junction transistors, offering enhanced performance when compared to metal oxide semiconductor field effect transistor, (MOSFET), devices, have been used to improve the performance of bipolar-complementary MOS, (BiCMOS), chips, specifically chips used for microprocessor applications. The enhanced performance of BJT devices, is a result of a faster switching frequency, offered via reductions in the base width of the BJT device. In addition reductions in RC delays, accomplished via the use conductive extrinsic base layers, as well as accomplished via capacitance reductions, in turn obtained via the use of micro-miniaturization processing of specific regions of the BJT device, have also allowed increased BJT performance to be realized.
This invention will describe a fabrication process for a BJT device in which only a single polysilicon layer is used, for the emitter level, while extrinsic base, and intrinsic base regions, are formed in an epitaxial silicon base layer, deposited on underlying silicon seed layer, and on an underlying N type, epitaxial layer, with the intrinsic base region either formed in an undoped, epitaxial silicon base layer, or contained in the deposited epitaxial silicon base layer. These features result in a reduction in BJT area, specifically the reduction of base-collector, as well as collector-substrate capacitance, thus reducing performance degrading RC delays. This invention will also describe procedures in which the epitaxial silicon base layer is a composite epitaxial layer, used for the intrinsic base region, comprised of either a boron doped, silicon layer, or a boron doped, silicon-germanium layer, which increases transistor switching frequency, (Ft), again resulting in enhanced performance. Prior art, such as Solheim, in U.S. Pat. No. 5,071,778, describes a process for improving the device characteristics of a BJT device, via a self-aligned collector implant. However that prior art does not describe the unique processing features used in this invention, resulting in improved BJT performance, such as an epitaxial silicon layer, providing for both an extrinsic and intrinsic base region.